module double_flop_synchronizer 
(
    input bclk,
    input a_in,
    output b_out
);
    (*ASYNC_REG = "yes"*)reg b_in1d,b_in2d;
    always @(posedge bclk) begin
        b_in1d <= a_in;
        b_in2d <= b_in1d;
    end
    assign b_out = b_in2d;

endmodule

module pulse_synchronizer
(
    input   aclk,
    input   a_p,
    input   bclk,
    output  b_p
);

reg a_level;
(*ASYNC_REG = "yes"*)reg bl1d, bl2d, b_level;

always @(posedge aclk)begin
    a_level <= a_level ^ a_p;
end
always @(posedge bclk)begin
    bl1d <= a_level;
    bl2d <= bl1d;
end
always @(posedge bclk)begin
    b_level <= bl2d;
end

assign b_p = bl2d ^ b_level;

endmodule